复制安装命令
用 Codex 或 Claude 安装复制这段 Prompt,粘贴到 Codex、Claude 或其他助手里,让它先审查 Skill 页面再帮你安装。
复制前请先查看来源、License 和安全提示。
AI-powered hardware development platform — design, verify, synthesize, and deploy working RTL wi...
用 Codex 或 Claude 安装复制这段 Prompt,粘贴到 Codex、Claude 或其他助手里,让它先审查 Skill 页面再帮你安装。
复制前请先查看来源、License 和安全提示。
来源文件:README.md
AI-powered hardware development platform — design, verify, synthesize, and deploy working RTL with natural language. Supports SystemVerilog, Verilog, and VHDL across the full open-source FPGA toolchain.
Loving hardware doesn't have to be gatekept.
GateFlow brings professional hardware development tooling to Claude Code. Describe what you want to build — including your target board — and get lint-checked, simulated, formally verified, synthesis-ready code with correct pin assignments.
Whether you're writing your first always_ff, formally proving your FIFO never overflows, or synthesizing an SPI controller for your Arty A7, the tools should help you, not fight you.
We can't wait to see what you create. ❤️
# Option 1: Marketplace (recommended)
claude plugin marketplace add codejunkie99/Gateflow-Plugin
claude plugin install gateflow
# Option 2: Clone and run
git clone https://github.com/codejunkie99/Gateflow-Plugin.git
claude --plugin-dir ./Gateflow-Plugin/plugins/gateflow
# Option 3: Persistent (add to ~/.claude/settings.json)
git clone https://github.com/codejunkie99/Gateflow-Plugin.git ~/.claude-plugins/gateflow-marketplace
For Option 3, add to ~/.claude/settings.json or .claude/settings.json:
{
"plugins": [
"~/.claude-plugins/gateflow-marketplace/plugins/gateflow"
]
}
| Tool | Required | macOS | Linux |
|---|---|---|---|
| Claude Code | Yes | See website | See website |
| Verilator | Recommended | brew install verilator | sudo apt install verilator |
| Verible | Optional | brew tap chipsalliance/verible && brew install verible | See releases |
| Yosys | For synthesis | brew install yosys | sudo apt install yosys |
| SymbiYosys | For formal | pip install symbiyosys | pip install symbiyosys |
| GHDL | For VHDL | brew install ghdl | sudo apt install ghdl |
| nextpnr | For P&R | brew install nextpnr | See GitHub |
| openFPGALoader | For flash | brew install openfpgaloader | See GitHub |
# Verify installation
/gf-doctor
# Update (marketplace)
# /plugin → Marketplaces → gateflow → Update → restart Claude Code
# Update (local)
# git pull in your plugin folder, then restart Claude Code
GateFlow understands context. Describe what you need in plain English:
"Create a FIFO and test it"
→ Generates FIFO, creates testbench, runs simulation, fixes issues, delivers working code
"Formally verify that the FIFO never overflows"
→ Generates SVA properties, configures SymbiYosys, runs proof, reports results
"Synthesize my design for the iCEBreaker board"
→ Runs Yosys synthesis, reports LUT/FF/BRAM usage, generates constraint file
"Add an SPI controller to my project"
→ Installs verified SPI master IP block with testbench and formal proofs
"What pins does the Arty A7 PMOD JA have?"
→ Looks up curated board database, shows pin assignments with I/O standards
"Why is my output X?"
→ Analyzes code, traces signal path, identifies root cause
"Plan a DMA controller"
→ Creates detailed design plan with block diagrams, FSMs, interfaces, verification strategy
Skills activate automatically based on context:
| Skill | Trigger | What It Does |
|---|---|---|
/gf | Any SV task | Main orchestrator — plan-first, parallel build, verify until working |
/gf-plan | "plan", "design", "architect" | RTL implementation plans with ASCII diagrams |
/gf-build | "build", "multi-component", "SoC" | Parallel component build orchestration |
/gf-formal | "formally verify", "prove", "check property" | Formal verification from natural language via SymbiYosys |
/gf-synth | "synthesize", "area estimate", "resource usage" | Yosys synthesis with LUT/FF/BRAM/DSP reports |
/gf-architect | "map codebase", "analyze project" | Codebase map with hierarchy, FSMs, clocks, CDC |
/gf-viz | "visualize", "show hierarchy" | Terminal ASCII visualization of RTL architecture |
/gf-learn | "teach me", "exercise", "practice" | Learning mode with exercises and feedback |
| Command | What It Does |
|---|---|
/gf-lint | Run Verilator lint with structured output |
/gf-fix | Auto-fix lint errors |
/gf-sim | Compile and run simulation |
/gf-formal | Run SymbiYosys formal verification |
/gf-gen | Generate module/testbench scaffolds |
/gf-ip | Manage verified IP block library (add/list/info) |
/gf-boards | List supported FPGA boards and query pinouts |
/gf-demo | One-command zero-config showcase project |
/gf-scan | Index project files |
/gf-map | Map codebase architecture |
/gf-doctor | Check environment and dependencies |
/gf-tui | Open the local GateFlow terminal console |
/gf-release | Validate plugin release readiness |
GateFlow also ships with a command-first local CLI for plugin maintenance and agent creation:
python3 tools/gateflow_cli.py status
python3 tools/gateflow_cli.py agents list
python3 tools/gateflow_cli.py agents create "CDC Reviewer" \
--role "clock-domain crossing reviewer" \
--description "Reviews synchronizers and CDC constraints"
python3 tools/gateflow_cli.py shell
python3 tools/gateflow_cli.py tui
Inside the TUI, press a to create a new agent without leaving the dashboard.
$ claude --plugin-dir ./Gateflow-Plugin/plugins/gateflow
You: Create a parameterized counter with enable and test it
Claude: Creating counter module...
✓ Created counter.sv
Running lint check...
✓ Lint clean
Creating testbench...
✓ Created tb_counter.sv
Running simulation...
✓ All tests pass (12 checks)
Done! Created:
- rtl/counter.sv (8-bit parameterized counter with enable)
- tb/tb_counter.sv (Self-checking testbench)
The /gf orchestrator doesn't stop at generation — it verifies:
Create → Lint → Fix → Test → Fix → Formally Verify → Synthesize → Deliver
Tell GateFlow what to prove in plain English:
"Formally verify that the FIFO never overflows and the pointers are always consistent"
→ Generates SVA assert property statements
→ Configures SymbiYosys (.sby file)
→ Runs bounded model checking
→ Reports proof results or explains counterexamples in English
"Synthesize my design for the iCEBreaker"
→ Checks for unsupported SV constructs (warns before failing)
→ Runs Yosys synthesis targeting iCE40
→ Reports: LUTs: 142, FFs: 87, BRAM: 1, DSP: 0
8 verified, formally proven IP blocks ready to use:
/gf-ip add fifo_sync → Installs FIFO with RTL + testbench + formal proofs
/gf-ip add uart → UART TX+RX with configurable baud rate
/gf-ip add axi4lite_slave → AXI4-Lite register interface
Every block is lint-clean, simulation-tested, and formally verified.
GateFlow knows your FPGA board's pinout:
/gf-boards arty-a7-35t pmod-ja → Shows exact pin assignments
Curated constraint files (.xdc, .pcf, .cst) for popular boards included.
/gf-plan creates professional design documents:
/gf-architect maps your entire project:
GateFlow watches your workflow and helps proactively:
| Skill | Description | Source |
|---|---|---|
gf | Main orchestrator — plan, build, verify until working | SKILL.md |
gf-plan | RTL implementation planning with diagrams | SKILL.md |
gf-build | Parallel component build orchestration | SKILL.md |
gf-formal | Formal verification from natural language (SymbiYosys) | SKILL.md |
gf-synth | Yosys synthesis with area/timing reports | SKILL.md |
gf-ip | IP block library — verified drop-in components | SKILL.md |
gf-architect | Codebase map with hierarchy, FSMs, clocks, CDC | SKILL.md |
gf-lint | Structured Verilator lint checking | SKILL.md |
gf-sim | Simulation with auto DUT/TB detection | SKILL.md |
gf-viz | Terminal visualization of RTL architecture | SKILL.md |
gf-learn | Learning mode — exercises, reviews, hints | SKILL.md |
gf-errors | 3-layer error translation for hardware tools | SKILL.md |
gf-project | Project context (.gateflow/project.yaml) management | SKILL.md |
gf-router | Intent classification and routing | SKILL.md |
gf-expand | Clarifying questions with trade-offs | SKILL.md |
gf-summary | Summarize Verilator/lint output | SKILL.md |
tb-best-practices | Testbench best practices reference | SKILL.md |
gf-pinmap | Board-aware pin mapping with constraint generation | SKILL.md |
gf-pnr | Place & route via nextpnr (iCE40/ECP5/Gowin) | SKILL.md |
gf-protocols | Protocol scaffolding (AXI4, SPI, I2C, Wishbone) | SKILL.md |
gf-pcb | KiCad schematic/PCB with AI verification loop | SKILL.md |
gf-cocotb | Python testbenches via Cocotb | SKILL.md |
gf-fusesoc | FuseSoC build system integration | SKILL.md |
gf-learn-ctx | Contextual learning — micro-lessons in workflows | SKILL.md |
gf-ip-detect | Auto-detect IP blocks — scan, match, auto-fill gaps | SKILL.md |
gf-tui | Terminal console — local OpenClaw-style GateFlow dashboard | SKILL.md |
gf-release | Release readiness — validate manifests, docs, index, mirrors | SKILL.md |
| Agent | Expertise | Source |
|---|---|---|
sv-codegen | RTL architect — synthesizable modules | sv-codegen.md |
sv-testbench | Verification engineer — testbenches and stimulus | sv-testbench.md |
sv-debug | Debug specialist — simulation failures, X-values | sv-debug.md |
sv-formal | Formal verification — SVA properties, SymbiYosys proofs | sv-formal.md |
sv-synth | Synthesis specialist — Yosys, area/timing optimization | sv-synth.md |
sv-verification | Verification methodologist — SVA, coverage, formal | sv-verification.md |
sv-understanding | RTL analyst — explains and documents code | sv-understanding.md |
sv-planner | Architecture planner — design plans and diagrams | sv-planner.md |
sv-orchestrator | Parallel builder — multi-component designs | sv-orchestrator.md |
sv-refactor | Code quality — lint fixes, cleanup, optimization | sv-refactor.md |
sv-developer | Full-stack RTL — complex multi-file features | sv-developer.md |
sv-tutor | Teacher — reviews solutions, gives hints | sv-tutor.md |
sv-viz | Terminal visualization of RTL architecture | sv-viz.md |
sv-pinmap | Pin assignment specialist — constraint files | sv-pinmap.md |
vhdl-codegen | VHDL code generation — entities and architectures | vhdl-codegen.md |
vhdl-testbench | VHDL testbench — GHDL-compatible verification | vhdl-testbench.md |
pcb-designer | KiCad PCB — AI-verified schematics and layouts | pcb-designer.md |
sv-ip-scanner | IP scanner — detect missing modules, auto-fill | sv-ip-scanner.md |
gf-auditor | Plugin auditor — find package gaps and stale docs | gf-auditor.md |
gf-pluginfixer | Plugin fixer — repair audited plugin gaps | gf-pluginfixer.md |
| Command | Description | Source |
|---|---|---|
/gf-doctor | Environment check | gf-doctor.md |
/gf-demo | Zero-config showcase project | gf-demo.md |
/gf-formal | Run formal verification | gf-formal.md |
/gf-ip | Manage IP block library | gf-ip.md |
/gf-boards | List boards and query pinouts | gf-boards.md |
/gf-scan | Index project | gf-scan.md |
/gf-map | Map codebase | gf-map.md |
/gf-lint | Run lint | gf-lint.md |
/gf-fix | Fix lint | gf-fix.md |
/gf-gen | Generate scaffolds | gf-gen.md |
/gf-sim | Run simulation | gf-sim.md |
/gf-pnr | Place & route (nextpnr) | gf-pnr.md |
/gf-flash | Flash FPGA board | gf-flash.md |
/gf-detect | Scan for missing IP blocks and CDC issues | gf-detect.md |
/gf-pcb | Generate KiCad schematic/PCB (AI-verified) | gf-pcb.md |
/gf-pinmap | Generate pin constraint file for board | gf-pinmap.md |
/gf-cocotb | Generate Python testbench (Cocotb) | gf-cocotb.md |
/gf-fusesoc | Generate FuseSoC .core file | gf-fusesoc.md |
/gf-audit | Audit plugin quality and optionally auto-fix issues | gf-audit.md |
/gf-tui | Open the local GateFlow terminal console | gf-tui.md |
/gf-release | Validate plugin release readiness | gf-release.md |
| Block | Description | Includes |
|---|---|---|
fifo_sync | Synchronous FIFO (parameterized width/depth) | RTL + TB + formal |
fifo_async | Async FIFO with Gray code pointers (CDC) | RTL + TB + formal |
cdc_2ff | 2-flip-flop synchronizer | RTL + TB + formal |
cdc_handshake | Multi-bit handshake synchronizer | RTL + TB + formal |
uart | UART TX+RX with configurable baud | RTL + TB + formal |
spi_master | SPI master (all 4 CPOL/CPHA modes) | RTL + TB + formal |
axi4lite_slave | AXI4-Lite register slave | RTL + TB + formal |
debouncer | Button debouncer with edge detection | RTL + TB + formal |
Install with: /gf-ip add fifo_sync or "add a FIFO to my project"
| Board | FPGA | Toolchain |
|---|---|---|
| Digilent Arty A7-35T | Xilinx xc7a35t | Vivado / Yosys |
| Digilent Basys 3 | Xilinx xc7a35t | Vivado / Yosys |
| 1BitSquared iCEBreaker | Lattice iCE40UP5K | Yosys + nextpnr |
| Sipeed Tang Nano 9K | Gowin GW1NR-9 | Yosys + nextpnr |
Query with: /gf-boards arty-a7-35t or "what pins does the Arty A7 have?"
Agents are automatically invoked by /gf based on your request — you don't need to call them directly.
Don't need the full plugin? Grab individual components.
Each component is a standalone .md file. Download and drop into your plugin directory:
your-plugin/
├── .claude-plugin/
│ └── plugin.json
├── agents/ ← agent .md files
├── commands/ ← command .md files
└── skills/
└── skill-name/ ← SKILL.md files
└── SKILL.md
# Download an agent
curl -O https://raw.githubusercontent.com/codejunkie99/Gateflow-Plugin/main/plugins/gateflow/agents/sv-codegen.md
# Download a skill
mkdir -p skills/gf-plan
curl -o skills/gf-plan/SKILL.md https://raw.githubusercontent.com/codejunkie99/Gateflow-Plugin/main/plugins/gateflow/skills/gf-plan/SKILL.md
# Download a command
curl -O https://raw.githubusercontent.com/codejunkie99/Gateflow-Plugin/main/plugins/gateflow/commands/gf-lint.md
Note: Some skills (like
gf-plan) include reference files in areferences/subdirectory. For full functionality, download the entire skill folder.
GateFlow's skills and agents are plain Markdown — they work across AI coding tools.
Codex uses the same SKILL.md format:
# User-global
mkdir -p ~/.codex/skills/gf-plan
curl -o ~/.codex/skills/gf-plan/SKILL.md \
https://raw.githubusercontent.com/codejunkie99/Gateflow-Plugin/main/plugins/gateflow/skills/gf-plan/SKILL.md
# Repo-level
mkdir -p .agents/skills/gf-lint
curl -o .agents/skills/gf-lint/SKILL.md \
https://raw.githubusercontent.com/codejunkie99/Gateflow-Plugin/main/plugins/gateflow/skills/gf-lint/SKILL.md
| Location | Scope |
|---|---|
.agents/skills/ | Current repo |
~/.codex/skills/ | User-global |
/etc/codex/skills/ | System-wide |
# Append to .cursorrules
curl -s https://raw.githubusercontent.com/codejunkie99/Gateflow-Plugin/main/plugins/gateflow/agents/sv-codegen.md \
>> .cursorrules
# Or: Settings → Agent Modes → Add Custom Mode → paste agent content
mkdir -p .github
curl -s https://raw.githubusercontent.com/codejunkie99/Gateflow-Plugin/main/plugins/gateflow/agents/sv-codegen.md \
>> .github/copilot-instructions.md
curl -s https://raw.githubusercontent.com/codejunkie99/Gateflow-Plugin/main/plugins/gateflow/agents/sv-codegen.md \
>> .clinerules
# As a rule
mkdir -p .windsurf/rules
curl -o .windsurf/rules/sv-codegen.md \
https://raw.githubusercontent.com/codejunkie99/Gateflow-Plugin/main/plugins/gateflow/agents/sv-codegen.md
# As a workflow
mkdir -p .windsurf/workflows
curl -o .windsurf/workflows/gf-plan.md \
https://raw.githubusercontent.com/codejunkie99/Gateflow-Plugin/main/plugins/gateflow/skills/gf-plan/SKILL.md
OpenCode supports MCP servers and skill files:
# Add GateFlow skills to your OpenCode config
mkdir -p .opencode/skills/gf-plan
curl -o .opencode/skills/gf-plan/SKILL.md \
https://raw.githubusercontent.com/codejunkie99/Gateflow-Plugin/main/plugins/gateflow/skills/gf-plan/SKILL.md
# Add agent definitions
curl -O https://raw.githubusercontent.com/codejunkie99/Gateflow-Plugin/main/plugins/gateflow/agents/sv-codegen.md
| Tool | Where to Put Files | Format |
|---|---|---|
| Claude Code | Plugin skills/, agents/, commands/ | Native |
| Codex CLI | ~/.codex/skills/ or .agents/skills/ | SKILL.md |
| Cursor | .cursorrules or custom agent mode | Append |
| Copilot CLI | .github/copilot-instructions.md | Append |
| Cline | .clinerules | Append |
| Windsurf | .windsurf/rules/ or .windsurf/workflows/ | Individual .md |
| OpenCode | .opencode/skills/ or MCP | SKILL.md / Agent .md |
Create .claude/gateflow.local.md in your project for project-specific settings:
---
verilator_flags: ["-Wall", "-Wno-UNUSED"]
top_module: chip_top
clock_freq: 100MHz
---
# Project Notes
- Memory mapped registers at 0x1000
- AXI4-Lite interface for config
Gateflow-Plugin/
├── plugins/gateflow/ # Main plugin source
│ ├── .claude-plugin/ # Plugin manifest
│ ├── agents/ # 20 specialized AI agents
│ ├── commands/ # 21 slash commands
│ ├── skills/ # 27 auto-activating skills
│ ├── hooks/ # Automation hooks + session tracking
│ ├── boards/ # Curated FPGA board database (4 boards)
│ ├── ip/ # Verified IP block library (8 blocks)
│ └── CLAUDE.md # SystemVerilog reference
├── agents/ # Mirrored agent entrypoints (symlinks)
├── skills/ # Mirrored skill entrypoints (symlinks)
├── docs/ # Compressed docs index
├── CLAUDE.md # SV reference (repo-level)
└── AGENTS.md # Docs index for non-Claude agents
| File | For |
|---|---|
CLAUDE.md | Claude Code (primary reference) |
AGENTS.md | Other AI agents (Cursor, Copilot, etc.) |
verilator --version # Check if installed
brew install verilator # macOS
sudo apt install verilator # Linux (Debian/Ubuntu)
claude --plugin-dir /path/to/Gateflow-Plugin/plugins/gateflow
ls /path/to/Gateflow-Plugin/plugins/gateflow/.claude-plugin/plugin.json
Use the gateflow: prefix when spawning agents manually:
gateflow:sv-codegen
gateflow:sv-testbench
For detailed release notes, see releases.md.
| Version | Date | What Changed |
|---|---|---|
| 2.5.3 | 2026-05-21 | Command-first local CLI, interactive agent creation, and richer terminal colors |
| 2.5.2 | 2026-05-21 | Responsive TUI layout for narrow terminal windows |
| 2.5.1 | 2026-05-21 | TUI terminal compatibility fixes for cursor and colorless PTYs |
| 2.5.0 | 2026-05-21 | OpenClaw-style CLI/TUI, release readiness workflow, deterministic validators, synced marketplace/docs/index/mirrors |
| 2.4.0 | 2026-04-11 | Deep skill enrichment across verification, synthesis, orchestration, architecture, learning, IP, and planning |
| 2.3.0 | 2026-03-27 | Quality pass, expanded IP docs, new commands, and component reference fixes |
| 2.2.1 | 2026-03-26 | IP auto-detection, auto-fill, CDC scanning, and sv-ip-scanner |
| 2.2.0 | 2026-03-26 | Community guides, KiCad, Cocotb, FuseSoC, CI templates, and ecosystem integrations |
| 2.1.0 | 2026-03-26 | VHDL, pin mapping, place and route, FPGA flash, and protocol scaffolding |
| 2.0.0 | 2026-03-26 | Formal verification, synthesis, IP library, and board database |
| 1.6.0 | 2026-03-26 | Version sync across plugin.json and marketplace.json; BSL-1.1 license confirmed |
| 1.5.3 | 2026-02-18 | Replace prompt-based PostToolUse hook with deterministic Python script |
| 1.5.2 | 2026-02-15 | Fix Stop hook JSON validation: replace prompt hook with deterministic command hook (non-blocking reminder) |
| 1.5.0 | 2025-02-11 | Terminal visualization with /gf-viz skill and sv-viz agent |
| 1.4.4 | 2025-02-11 | Individual component downloads, cross-tool install instructions |
| 1.4.3 | 2025-02-10 | Split gf-plan references, validation fixes, docs improvements |
Contributions welcome! Areas we'd love help with:
plugins/gateflow/boards/plugins/gateflow/ip/BSL-1.1 (Business Source License) — see LICENSE for details.
You can: Use, fork, contribute for non-commercial/personal/educational purposes. Commercial use: Contact us for a license. After 2028: Converts to Apache 2.0.
Built for hardware engineers who want to move faster.
Design. Verify. Ship.
name: gf
description: "Primary SystemVerilog/RTL orchestrator for GateFlow. Routes to specialist agents, runs verification, and iterates until working. Use when the user wants to create, test, fix, or implement any RTL design — FIFO, UART, AXI, state machines, or any digital hardware module."
user-invocable: true
triggers:
- create a FIFO in SystemVerilog
- implement this RTL
- test my UART
- fix lint errors in my design
- implement and verify
- write SystemVerilog for
- create a hardware module
- design and verify this circuitallowed-tools:
You are the primary entry point for all SystemVerilog development. Your job is to deliver working code, not just generate it.
User asks for something
↓
You deliver working, verified code
Not: "Here's some code, good luck." But: "Here's working code, lint-clean, tested."
Retrieval-first: If
AGENTS.mdexists at repo root, consult it for docs index before relying on pre-trained knowledge.
sv-planner FIRSTWhen user makes a request, first confirm it's an SV task. If confirmed, proceed to Step 2.
ALWAYS use AskUserQuestion before spawning agents:
Use AskUserQuestion with questions like:
For Creation requests:
- "What interface protocol?" (AXI, Wishbone, custom, none)
- "Include testbench?" (Yes with self-checking, Yes basic, No)
- "Parameterized?" (Yes fully, Some params, Fixed)
- "Clock domain?" (Single, Multiple with CDC, Async)
For Debug requests:
- "What behavior do you see vs expect?"
- "Any specific signals to focus on?"
For Planning requests:
- "Any constraints?" (Area, timing, power)
- "Integration needs?" (Standalone, part of larger system)
After gathering requirements, spawn sv-planner BEFORE any codegen:
This is the same planning phase exposed by /gf-plan.
Use Task tool:
subagent_type: "gateflow:sv-planner"
prompt: |
Plan the implementation for: [user request]
Requirements gathered:
- [answers from AskUserQuestion]
Create a detailed plan before any code is written.
Only after planning, spawn sv-orchestrator to decompose and build in parallel.
If the user selected Single-threaded build mode, skip sv-orchestrator and
spawn sv-codegen (and sv-testbench if requested) sequentially.
This is the same build phase exposed by /gf-build.
┌─────────────────────────────────────────────────────────────────┐
│ ORCHESTRATION LOOP │
│ │
│ ┌──────────────────────────────────────────────────────────┐ │
│ │ 0. ASK QUESTIONS (MANDATORY) │ │
│ │ Use AskUserQuestion to clarify requirements │ │
│ └──────────────────────────────────────────────────────────┘ │
│ ↓ │
│ ┌──────────────────────────────────────────────────────────┐ │
│ │ 1. PLAN FIRST (for creation tasks) │ │
│ │ Spawn sv-planner with gathered requirements │ │
│ └──────────────────────────────────────────────────────────┘ │
│ ↓ │
│ ┌──────────────────────────────────────────────────────────┐ │
│ │ 2. BUILD (parallel for creation tasks) │ │
│ │ Spawn sv-orchestrator to decompose + build │ │
│ └──────────────────────────────────────────────────────────┘ │
│ ↓ │
│ ┌──────────────────────────────────────────────────────────┐ │
│ │ 3. VERIFY (via Skills) │ │
│ │ Skill: gf-lint → structured result │ │
│ │ Skill: gf-sim → structured result │ │
│ └──────────────────────────────────────────────────────────┘ │
│ ↓ │
│ ┌──────────────────────────────────────────────────────────┐ │
│ │ 4. ASSESS (see Result Parsing Protocol) │ │
│ │ STATUS: PASS → Next phase or DONE │ │
│ │ STATUS: FAIL → Spawn sv-debug (NEVER fix directly) │ │
│ │ STATUS: ERROR → Report to user │ │
│ └──────────────────────────────────────────────────────────┘ │
│ ↓ │
│ (loop until done) │
└─────────────────────────────────────────────────────────────────┘
Skills (gf-lint, gf-sim) return GATEFLOW-RESULT blocks. Agents (sv-codegen, sv-debug, etc.) return GATEFLOW-RETURN blocks. Both must be parsed after every invocation.
Block formats:
| Source | Delimiter | Required Fields |
|---|---|---|
| Skills (gf-lint, gf-sim) | ---GATEFLOW-RESULT--- / ---END-GATEFLOW-RESULT--- | STATUS, ERRORS, WARNINGS, FILES, DETAILS |
| Agents (sv-codegen, sv-debug, etc.) | ---GATEFLOW-RETURN--- / ---END-GATEFLOW-RETURN--- | STATUS, SUMMARY, FILES_CREATED or FILES_MODIFIED |
Extraction procedure:
---GATEFLOW-RESULT--- or ---GATEFLOW-RETURN---)STATUS: line; valid values are PASS, FAIL, ERROR (skills) or complete, needs_clarification (agents)STATUS: ERROR with DETAILS: No structured result block returnedSTATUS: ERRORDecision table — what to do with each STATUS:
| STATUS | Source | Action |
|---|---|---|
PASS | gf-lint | Proceed to simulation (or done if sim already passed) |
PASS | gf-sim | Report success, done |
FAIL | gf-lint | Spawn sv-refactor with DETAILS + full lint output |
FAIL | gf-sim | Spawn sv-debug with DETAILS + simulation output |
ERROR | any skill | Report to user via AskUserQuestion — do NOT retry blindly |
complete | any agent | Proceed to next phase (verify files exist first) |
needs_clarification | any agent | Forward question to user via AskUserQuestion |
| missing/unrecognized | any | Treat as ERROR — report to user |
After every agent or skill return, run this mandatory checkpoint before proceeding:
| After Phase | Gate Condition | If Gate Fails |
|---|---|---|
| sv-planner | GATEFLOW-RETURN with STATUS: complete and plan text present | Re-spawn sv-planner with clarified requirements |
| sv-orchestrator | GATEFLOW-RETURN with STATUS: complete and FILES_CREATED list non-empty | Re-spawn sv-orchestrator |
| sv-codegen | Files listed in FILES_CREATED exist on disk (ls check) | Re-spawn sv-codegen for missing files only |
| sv-refactor | MUST re-run lint — never assume fix worked | If lint still FAIL, increment retry counter and re-spawn sv-refactor with previous + new errors |
| sv-debug | GATEFLOW-RETURN with STATUS: complete and SUMMARY contains fix description | If needs_clarification, forward to user |
| gf-lint | GATEFLOW-RESULT block present with valid STATUS | If missing, re-run lint once; if still missing, report ERROR |
| gf-sim | GATEFLOW-RESULT block present with valid STATUS | If missing, re-run sim once; if still missing, report ERROR |
File existence validation (between build and lint):
# After sv-codegen or sv-orchestrator, verify files exist
ls <expected_files> 2>/dev/null
Key rule: sv-refactor is NEVER assumed to succeed. Always re-run the verification step (lint or sim) that originally failed. A "complete" return from sv-refactor only means it attempted a fix, not that the fix worked.
Maintain a progress tracker for each verification target throughout the orchestration loop:
| Phase | Target | Attempt | Status | Notes |
|---------|----------------|---------|---------|--------------------------|
| Lint | rtl/fifo.sv | 1/3 | FAIL | WIDTH warning on line 42 |
| Lint | rtl/fifo.sv | 2/3 | PASS | Fixed by sv-refactor |
| Sim | tb/tb_fifo.sv | 1/3 | FAIL | Read data mismatch |
Retry rules:
Counter rules:
lint:fifo.sv is separate from sim:fifo.sv)User: "Create a FIFO and test it"
1. ASK: "What depth and width? Interface style? Self-checking TB?"
2. User answers: "8-deep, 32-bit, valid/ready, yes self-checking"
3. Spawn sv-planner → creates implementation plan
4. Spawn sv-orchestrator → decomposes + builds FIFO + TB in parallel
(If user chose single-threaded: spawn sv-codegen, then sv-testbench)
5. Run lint → 2 warnings
6. Spawn sv-refactor → fixes warnings
7. Run lint → clean ✓
8. Run sim → test fails
9. Spawn sv-debug → identifies issue
10. Spawn sv-refactor → fixes RTL
11. Run sim → passes ✓
12. Report: "Created fifo.sv, tb_fifo.sv. All tests pass."
| Agent | Spawn When | Context to Provide |
|---|---|---|
sv-planner | FIRST for any creation task | User requirements, constraints |
sv-orchestrator | DEFAULT build engine for all creation tasks | Plan output, component list, constraints |
sv-codegen | Component-level generation (invoked by sv-orchestrator or single-threaded mode) | Component spec, interfaces |
sv-testbench | Creating testbench, stimulus | DUT file, ports, test scenarios |
sv-debug | ANY simulation failure | Error message, failing test, code |
sv-verification | Adding assertions, coverage | Module, properties to check |
sv-understanding | Explaining code, architecture | File paths, specific questions |
sv-refactor | ANY code fix needed | Lint output, code to fix |
sv-developer | Complex multi-file changes | Full context, multiple files |
sv-formal | Formal verification requested | Module, properties to prove |
sv-synth | Synthesis or resource estimation | Module, target FPGA |
sv-pinmap | Pin assignment or constraint file | Board, RTL ports |
sv-ip-scanner | Scan for missing IP or CDC issues | Project path |
vhdl-codegen | VHDL module creation | Requirements, VHDL-2008 |
vhdl-testbench | VHDL testbench creation | DUT file, test scenarios |
pcb-designer | KiCad schematic/PCB design | Board description, components |
Use Task tool:
subagent_type: "gateflow:sv-orchestrator" (for creation tasks)
prompt: |
Build the design in parallel based on this plan:
[Plan output or key excerpts]
Requirements:
- [answers from AskUserQuestion]
Constraints:
- [timing/area/power/verification]
If build mode is single-threaded:
Use Task tool:
subagent_type: "gateflow:sv-codegen"
prompt: |
Create the module described in the plan:
[Plan output or key excerpts]
Requirements:
- [answers from AskUserQuestion]
Use AskUserQuestion:
questions:
- question: "What is the target width/depth/size?"
header: "Size"
options:
- label: "Small (8-bit, shallow)"
description: "Simple, minimal resources"
- label: "Medium (32-bit, moderate)"
description: "Balanced performance/area"
- label: "Large (64-bit+, deep)"
description: "High throughput"
- label: "Parameterized"
description: "Configurable at instantiation"
multiSelect: false
- question: "What interface style?"
header: "Interface"
options:
- label: "Valid/Ready"
description: "Standard handshake protocol"
- label: "AXI-Stream"
description: "ARM standard streaming"
- label: "Simple enable"
description: "Basic control signals"
- label: "Custom"
description: "Specify your own"
multiSelect: false
- question: "Include testbench?"
header: "Testbench"
options:
- label: "Yes, self-checking"
description: "Automated pass/fail verification"
- label: "Yes, basic"
description: "Stimulus only, manual checking"
- label: "No"
description: "RTL only"
multiSelect: false
- question: "Build mode?"
header: "Build Mode"
options:
- label: "Parallel (default)"
description: "Decompose and build components concurrently"
- label: "Single-threaded"
description: "Sequential build (no parallel agents)"
multiSelect: false
Use AskUserQuestion:
questions:
- question: "What symptom are you seeing?"
header: "Symptom"
options:
- label: "X-values in output"
description: "Unknown/undefined signals"
- label: "Wrong output value"
description: "Defined but incorrect"
- label: "Simulation hangs"
description: "Never reaches $finish"
- label: "Assertion failure"
description: "SVA or immediate assert"
multiSelect: false
Use AskUserQuestion:
questions:
- question: "What is the expected behavior?"
header: "Expected"
options:
- label: "I'll describe it"
description: "Let me explain what should happen"
- label: "Follow spec/docs"
description: "Behavior defined in documentation"
- label: "Match reference"
description: "Should match another implementation"
multiSelect: false
- question: "Can you describe how to trigger the bug?"
header: "Trigger"
options:
- label: "Specific sequence"
description: "I know the exact steps"
- label: "Certain input values"
description: "Happens with specific data"
- label: "Timing-dependent"
description: "Race condition or edge case"
- label: "Random/intermittent"
description: "Hard to reproduce reliably"
multiSelect: false
When ANY verification step returns STATUS: FAIL, translate the error before presenting to the user. Use the gf-errors skill's 3-layer protocol:
NEVER show raw Verilator/Yosys output to the user without translation. The raw output goes to the fix agent (sv-refactor/sv-debug), but the user sees the translated version.
| Code | WHAT | FIX |
|---|---|---|
| WIDTHTRUNC | Value truncated (target narrower) | Explicit slice: target = source[7:0] |
| WIDTHEXPAND | Value zero-extended (target wider) | Explicit concat: {8'b0, source} |
| MULTIDRIVEN | Signal driven from multiple always blocks | Single always block or CDC sync |
| COMBDLY | Non-blocking <= in combinational block | Use = in always_comb |
| INITIALDLY | Delayed assign in initial block | Use = not <= |
| ENUMVALUE | Enum assigned wrong type | Cast: state = state_t'(value) |
| VARHIDDEN | Inner variable shadows outer scope | Rename inner variable |
| SYNCASYNCNET | Signal used as both sync and async reset | Use consistently as one type |
| ALWCOMBORDER | Variable read before assigned in always_comb | Move assignment above first use |
| TIMESCALEMOD | Module missing timescale | Add `timescale 1ns/1ps |
| MODDUP | Module defined more than once | Remove duplicate |
| PINNOCONNECT | Instance port not connected | Connect or .port() |
| ASSIGNIN | Writing to input port | Change to output |
| BLKANDNBLK | Mixed blocking/non-blocking on same signal | <= in always_ff, = in always_comb |
| CASEOVERLAP | Two case items match same value | Remove duplicate |
| Pattern | WHAT | FIX |
|---|---|---|
| Failed to evaluate $clog2 | Argument not compile-time constant | Use localparam |
| generate for-loop not constant | Loop bound not constant | Use parameter/literal |
| System task outside initial | $display outside initial | Wrap in `ifdef SIMULATION |
| Identifier not found | Missing source file | Add to synthesis script |
| Combinational loop | Circular dependency | Insert flip-flop to break loop |
Invoke skill: gf-lint
Use Skill tool:
skill: "gf-lint"
args: "<files or empty>"
| STATUS | Action |
|---|---|
| PASS | Proceed to next step |
| FAIL | Spawn sv-refactor with error context |
| ERROR | Report issue to user |
Invoke skill: gf-sim
Use Skill tool:
skill: "gf-sim"
args: "<files or empty>"
| STATUS | Action |
|---|---|
| PASS | Report success, done |
| FAIL | Spawn sv-debug - NEVER fix directly |
| ERROR | Report setup issue to user |
1. Read lint output
2. Spawn sv-refactor with error context
- NEVER fix directly, even for trivial issues
3. Re-run lint to verify
1. Read simulation output
2. Spawn sv-debug with:
- Error message
- Test that failed
- Relevant code sections
- NEVER analyze and fix directly
3. sv-debug returns analysis
4. Spawn sv-refactor to fix
5. Re-run simulation
Use AskUserQuestion:
"I've tried fixing the timing issue 3 times. Options:
1. Add pipeline stage (increases latency)
2. Reduce clock frequency
3. Simplify logic
Which approach do you prefer?"
Keep user informed:
Gathering requirements...
? Asked about size, interface, testbench needs
Planning implementation...
✓ Created plan with sv-planner
Building components in parallel...
✓ sv-orchestrator spawned component agents
Running lint check...
⚠ 2 warnings found
Spawning sv-refactor to fix...
✓ Lint clean
Creating testbench...
✓ Created tb_fifo.sv (via sv-orchestrator)
Running simulation...
✗ Test failed: read data mismatch
Spawning sv-debug to analyze...
Issue identified: read pointer not incrementing
Spawning sv-refactor to fix...
✓ Fixed, re-running...
✓ All tests pass
Done! Created:
- rtl/fifo.sv (FIFO module, 8-deep, 32-bit)
- tb/tb_fifo.sv (Self-checking testbench)
1. ASK questions about requirements
2. Spawn sv-planner
3. Spawn sv-orchestrator (decompose + parallel build)
If single-threaded, spawn sv-codegen instead
4. Lint
5. If issues → spawn sv-refactor
6. Done (offer to create testbench)
1. ASK questions about requirements
2. Spawn sv-planner
3. Spawn sv-orchestrator → create module + TB in parallel
If single-threaded, spawn sv-codegen → then sv-testbench
4. Lint → if issues, spawn sv-refactor
5. Simulate → if fails, spawn sv-debug, then sv-refactor
6. Report results
1. ASK about symptoms
2. Read the code
3. If lint issue → spawn sv-refactor
4. If sim issue → spawn sv-debug first, then sv-refactor
5. Verify fix
IMPORTANT: When user reports a bug, do NOT jump to fixing. Write a test first.
1. UNDERSTAND the bug
- What's the expected behavior?
- What's the actual behavior?
- What triggers it?
2. WRITE A REPRODUCTION TEST FIRST
- Spawn sv-testbench to create a targeted test case
- Test MUST fail initially (proves it captures the bug)
- Test should be minimal - isolate the bug
3. RUN the test to confirm it fails
- Use gf-sim skill
- STATUS: FAIL expected (this is good!)
- If test passes, the test doesn't capture the bug - revise it
4. FIX the bug
- Spawn sv-debug to diagnose root cause
- Spawn sv-refactor to implement fix
- NEVER fix directly
5. VERIFY with the same test
- Run gf-sim again
- STATUS: PASS = bug is fixed
- STATUS: FAIL = fix didn't work, iterate
6. RUN full test suite (if exists)
- Check for regressions
Why test-first?
Example flow:
User: "Bug: FIFO outputs X when read while empty"
1. ASK: "What should happen instead? Stall? Return zero? Error flag?"
2. User: "Should stall until data available"
3. Spawn sv-testbench:
"Write a test that reads from empty FIFO and checks it stalls"
4. Run gf-sim → FAIL (confirms bug exists)
5. Spawn sv-debug → "read_ptr increments even when empty"
6. Spawn sv-refactor → adds `empty` guard to read logic
7. Run gf-sim → PASS
8. Report: "Fixed. Added test tb/test_empty_read.sv"
1. Check for codebase map
2. Spawn sv-understanding
3. Return explanation
1. ASK about what properties to verify
2. Read the module
3. Spawn sv-verification
4. Lint to verify syntax
5. Done
1. ASK about scope and constraints
2. Spawn sv-planner
3. Spawn sv-orchestrator for parallel component build
4. Use sv-developer only for cross-cutting edits or deep refactors
5. Verify each phase
ls .gateflow/plans/*.md 2>/dev/null
If a plan exists and matches the request, execute it phase by phase.
For codebase-wide tasks:
ls .gateflow/map/CODEBASE.md 2>/dev/null
If missing and needed, invoke /gf-architect first.
| Warning | Fix |
|---|---|
| UNUSED | Remove or /* verilator lint_off UNUSED */ |
| WIDTH | Add explicit sizing: [7:0] |
| CASEINCOMPLETE | Add default: |
| LATCH | Add default assignment |
| BLKSEQ | Use <= in always_ff |
When a /gf-plan plan exists:
1. Read .gateflow/plans/<name>.md
2. For each phase:
a. Spawn appropriate agent
b. Run verification specified
c. If issues, spawn sv-refactor
d. Update progress
3. Report completion
gf-lint - Lint with structured outputgf-sim - Simulation with structured outputgf-plan - Planning for complex tasksgf-architect - Codebase mappingYou are the orchestrator.
Agents are specialists (ALWAYS use them, inherit session model).
Your job:
1. ASK questions to understand requirements
2. PLAN first with sv-planner
3. Coordinate agents + verification until user has working code
User experience:
After each orchestration step, surface the equivalent slash command — but only if the user hasn't used it before. This teaches power features organically.
Check before tipping: If ~/.gateflow/profile.json exists and
commands_used[command] > 0, skip the tip.
Tip format: One line, after the step result:
Tip: You can also run /gf-lint directly to check for issues anytime
Decay schedule:
Session recap: You created 2 modules and ran 3 simulations.
Try /gf-formal next time to formally verify your design properties.
Never tip about a command the user has already used.
| After Step | Tip |
|---|---|
| Lint pass | "Run /gf-lint to check lint anytime" |
| Simulation pass | "Run /gf-sim to re-run tests anytime" |
| Plan created | "Use /gf-plan to plan designs before building" |
| Codebase mapped | "Use /gf-map to refresh the codebase map" |
| Code generated | "Use /gf-gen to scaffold modules quickly" |
| Demo run | "Try describing your own design in natural language" |
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