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AI-powered hardware development platform — design, verify, synthesize, and deploy working RTL wi...

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项目 README

来源文件:README.md

抓取于 2026年7月29日

GateFlow Plugin for Claude Code

AI-powered hardware development platform — design, verify, synthesize, and deploy working RTL with natural language. Supports SystemVerilog, Verilog, and VHDL across the full open-source FPGA toolchain.

GitHub Stars Version License: BSL-1.1 Claude Code Plugin

GateFlow Demo

GateFlow v2.3.1 Update


Loving hardware doesn't have to be gatekept.

GateFlow brings professional hardware development tooling to Claude Code. Describe what you want to build — including your target board — and get lint-checked, simulated, formally verified, synthesis-ready code with correct pin assignments.

Whether you're writing your first always_ff, formally proving your FIFO never overflows, or synthesizing an SPI controller for your Arty A7, the tools should help you, not fight you.

We can't wait to see what you create. ❤️



Quick Start

Install

# Option 1: Marketplace (recommended)
claude plugin marketplace add codejunkie99/Gateflow-Plugin
claude plugin install gateflow

# Option 2: Clone and run
git clone https://github.com/codejunkie99/Gateflow-Plugin.git
claude --plugin-dir ./Gateflow-Plugin/plugins/gateflow

# Option 3: Persistent (add to ~/.claude/settings.json)
git clone https://github.com/codejunkie99/Gateflow-Plugin.git ~/.claude-plugins/gateflow-marketplace

For Option 3, add to ~/.claude/settings.json or .claude/settings.json:

{
  "plugins": [
    "~/.claude-plugins/gateflow-marketplace/plugins/gateflow"
  ]
}

Prerequisites

ToolRequiredmacOSLinux
Claude CodeYesSee websiteSee website
VerilatorRecommendedbrew install verilatorsudo apt install verilator
VeribleOptionalbrew tap chipsalliance/verible && brew install veribleSee releases
YosysFor synthesisbrew install yosyssudo apt install yosys
SymbiYosysFor formalpip install symbiyosyspip install symbiyosys
GHDLFor VHDLbrew install ghdlsudo apt install ghdl
nextpnrFor P&Rbrew install nextpnrSee GitHub
openFPGALoaderFor flashbrew install openfpgaloaderSee GitHub

Verify & Update

# Verify installation
/gf-doctor

# Update (marketplace)
# /plugin → Marketplaces → gateflow → Update → restart Claude Code

# Update (local)
# git pull in your plugin folder, then restart Claude Code

Usage

Just Ask

GateFlow understands context. Describe what you need in plain English:

"Create a FIFO and test it"
 → Generates FIFO, creates testbench, runs simulation, fixes issues, delivers working code

"Formally verify that the FIFO never overflows"
 → Generates SVA properties, configures SymbiYosys, runs proof, reports results

"Synthesize my design for the iCEBreaker board"
 → Runs Yosys synthesis, reports LUT/FF/BRAM usage, generates constraint file

"Add an SPI controller to my project"
 → Installs verified SPI master IP block with testbench and formal proofs

"What pins does the Arty A7 PMOD JA have?"
 → Looks up curated board database, shows pin assignments with I/O standards

"Why is my output X?"
 → Analyzes code, traces signal path, identifies root cause

"Plan a DMA controller"
 → Creates detailed design plan with block diagrams, FSMs, interfaces, verification strategy

Skills (Auto-Activating)

Skills activate automatically based on context:

SkillTriggerWhat It Does
/gfAny SV taskMain orchestrator — plan-first, parallel build, verify until working
/gf-plan"plan", "design", "architect"RTL implementation plans with ASCII diagrams
/gf-build"build", "multi-component", "SoC"Parallel component build orchestration
/gf-formal"formally verify", "prove", "check property"Formal verification from natural language via SymbiYosys
/gf-synth"synthesize", "area estimate", "resource usage"Yosys synthesis with LUT/FF/BRAM/DSP reports
/gf-architect"map codebase", "analyze project"Codebase map with hierarchy, FSMs, clocks, CDC
/gf-viz"visualize", "show hierarchy"Terminal ASCII visualization of RTL architecture
/gf-learn"teach me", "exercise", "practice"Learning mode with exercises and feedback

Commands

CommandWhat It Does
/gf-lintRun Verilator lint with structured output
/gf-fixAuto-fix lint errors
/gf-simCompile and run simulation
/gf-formalRun SymbiYosys formal verification
/gf-genGenerate module/testbench scaffolds
/gf-ipManage verified IP block library (add/list/info)
/gf-boardsList supported FPGA boards and query pinouts
/gf-demoOne-command zero-config showcase project
/gf-scanIndex project files
/gf-mapMap codebase architecture
/gf-doctorCheck environment and dependencies
/gf-tuiOpen the local GateFlow terminal console
/gf-releaseValidate plugin release readiness

Local CLI

GateFlow also ships with a command-first local CLI for plugin maintenance and agent creation:

python3 tools/gateflow_cli.py status
python3 tools/gateflow_cli.py agents list
python3 tools/gateflow_cli.py agents create "CDC Reviewer" \
  --role "clock-domain crossing reviewer" \
  --description "Reviews synchronizers and CDC constraints"
python3 tools/gateflow_cli.py shell
python3 tools/gateflow_cli.py tui

Inside the TUI, press a to create a new agent without leaving the dashboard.

Example Session

$ claude --plugin-dir ./Gateflow-Plugin/plugins/gateflow

You: Create a parameterized counter with enable and test it

Claude: Creating counter module...
✓ Created counter.sv

Running lint check...
✓ Lint clean

Creating testbench...
✓ Created tb_counter.sv

Running simulation...
✓ All tests pass (12 checks)

Done! Created:
- rtl/counter.sv (8-bit parameterized counter with enable)
- tb/tb_counter.sv (Self-checking testbench)

Features

Working Code, Not Just Generated Code

The /gf orchestrator doesn't stop at generation — it verifies:

Create → Lint → Fix → Test → Fix → Formally Verify → Synthesize → Deliver

Formal Verification from Natural Language

Tell GateFlow what to prove in plain English:

"Formally verify that the FIFO never overflows and the pointers are always consistent"
 → Generates SVA assert property statements
 → Configures SymbiYosys (.sby file)
 → Runs bounded model checking
 → Reports proof results or explains counterexamples in English

Yosys Synthesis with Resource Reports

"Synthesize my design for the iCEBreaker"
 → Checks for unsupported SV constructs (warns before failing)
 → Runs Yosys synthesis targeting iCE40
 → Reports: LUTs: 142, FFs: 87, BRAM: 1, DSP: 0

Drop-In IP Library

8 verified, formally proven IP blocks ready to use:

/gf-ip add fifo_sync    → Installs FIFO with RTL + testbench + formal proofs
/gf-ip add uart          → UART TX+RX with configurable baud rate
/gf-ip add axi4lite_slave → AXI4-Lite register interface

Every block is lint-clean, simulation-tested, and formally verified.

Board-Aware Development

GateFlow knows your FPGA board's pinout:

/gf-boards arty-a7-35t pmod-ja  → Shows exact pin assignments

Curated constraint files (.xdc, .pcf, .cst) for popular boards included.

Hardware Design Planning

/gf-plan creates professional design documents:

  • Block diagrams (ASCII and Mermaid)
  • Module hierarchy and interface specs
  • FSM state diagrams
  • Clock domain analysis
  • Verification strategy and implementation phases

Codebase Intelligence

/gf-architect maps your entire project:

  • Module hierarchy and dependencies
  • Signal flow analysis and FSM extraction
  • Clock domain crossing detection
  • Package and type definitions

Comprehensive Coverage

  • Memory: FIFOs, dual-port RAM, register files
  • Error handling: ECC, watchdogs, TMR
  • DFT: Scan chains, JTAG, BIST
  • Timing: Retiming, pipelining, SDC
  • Verification: SVA, coverage, formal

Smart Hooks

GateFlow watches your workflow and helps proactively:

  • After SV edits — reminds you to lint
  • Before destructive commands — warns if you're about to delete SV files
  • On session end — checks if you forgot to lint or simulate modified files
  • Progressive tips — surfaces slash commands you haven't used yet

Components

Skills (27)

SkillDescriptionSource
gfMain orchestrator — plan, build, verify until workingSKILL.md
gf-planRTL implementation planning with diagramsSKILL.md
gf-buildParallel component build orchestrationSKILL.md
gf-formalFormal verification from natural language (SymbiYosys)SKILL.md
gf-synthYosys synthesis with area/timing reportsSKILL.md
gf-ipIP block library — verified drop-in componentsSKILL.md
gf-architectCodebase map with hierarchy, FSMs, clocks, CDCSKILL.md
gf-lintStructured Verilator lint checkingSKILL.md
gf-simSimulation with auto DUT/TB detectionSKILL.md
gf-vizTerminal visualization of RTL architectureSKILL.md
gf-learnLearning mode — exercises, reviews, hintsSKILL.md
gf-errors3-layer error translation for hardware toolsSKILL.md
gf-projectProject context (.gateflow/project.yaml) managementSKILL.md
gf-routerIntent classification and routingSKILL.md
gf-expandClarifying questions with trade-offsSKILL.md
gf-summarySummarize Verilator/lint outputSKILL.md
tb-best-practicesTestbench best practices referenceSKILL.md
gf-pinmapBoard-aware pin mapping with constraint generationSKILL.md
gf-pnrPlace & route via nextpnr (iCE40/ECP5/Gowin)SKILL.md
gf-protocolsProtocol scaffolding (AXI4, SPI, I2C, Wishbone)SKILL.md
gf-pcbKiCad schematic/PCB with AI verification loopSKILL.md
gf-cocotbPython testbenches via CocotbSKILL.md
gf-fusesocFuseSoC build system integrationSKILL.md
gf-learn-ctxContextual learning — micro-lessons in workflowsSKILL.md
gf-ip-detectAuto-detect IP blocks — scan, match, auto-fill gapsSKILL.md
gf-tuiTerminal console — local OpenClaw-style GateFlow dashboardSKILL.md
gf-releaseRelease readiness — validate manifests, docs, index, mirrorsSKILL.md

Agents (20)

AgentExpertiseSource
sv-codegenRTL architect — synthesizable modulessv-codegen.md
sv-testbenchVerification engineer — testbenches and stimulussv-testbench.md
sv-debugDebug specialist — simulation failures, X-valuessv-debug.md
sv-formalFormal verification — SVA properties, SymbiYosys proofssv-formal.md
sv-synthSynthesis specialist — Yosys, area/timing optimizationsv-synth.md
sv-verificationVerification methodologist — SVA, coverage, formalsv-verification.md
sv-understandingRTL analyst — explains and documents codesv-understanding.md
sv-plannerArchitecture planner — design plans and diagramssv-planner.md
sv-orchestratorParallel builder — multi-component designssv-orchestrator.md
sv-refactorCode quality — lint fixes, cleanup, optimizationsv-refactor.md
sv-developerFull-stack RTL — complex multi-file featuressv-developer.md
sv-tutorTeacher — reviews solutions, gives hintssv-tutor.md
sv-vizTerminal visualization of RTL architecturesv-viz.md
sv-pinmapPin assignment specialist — constraint filessv-pinmap.md
vhdl-codegenVHDL code generation — entities and architecturesvhdl-codegen.md
vhdl-testbenchVHDL testbench — GHDL-compatible verificationvhdl-testbench.md
pcb-designerKiCad PCB — AI-verified schematics and layoutspcb-designer.md
sv-ip-scannerIP scanner — detect missing modules, auto-fillsv-ip-scanner.md
gf-auditorPlugin auditor — find package gaps and stale docsgf-auditor.md
gf-pluginfixerPlugin fixer — repair audited plugin gapsgf-pluginfixer.md

Commands (21)

CommandDescriptionSource
/gf-doctorEnvironment checkgf-doctor.md
/gf-demoZero-config showcase projectgf-demo.md
/gf-formalRun formal verificationgf-formal.md
/gf-ipManage IP block librarygf-ip.md
/gf-boardsList boards and query pinoutsgf-boards.md
/gf-scanIndex projectgf-scan.md
/gf-mapMap codebasegf-map.md
/gf-lintRun lintgf-lint.md
/gf-fixFix lintgf-fix.md
/gf-genGenerate scaffoldsgf-gen.md
/gf-simRun simulationgf-sim.md
/gf-pnrPlace & route (nextpnr)gf-pnr.md
/gf-flashFlash FPGA boardgf-flash.md
/gf-detectScan for missing IP blocks and CDC issuesgf-detect.md
/gf-pcbGenerate KiCad schematic/PCB (AI-verified)gf-pcb.md
/gf-pinmapGenerate pin constraint file for boardgf-pinmap.md
/gf-cocotbGenerate Python testbench (Cocotb)gf-cocotb.md
/gf-fusesocGenerate FuseSoC .core filegf-fusesoc.md
/gf-auditAudit plugin quality and optionally auto-fix issuesgf-audit.md
/gf-tuiOpen the local GateFlow terminal consolegf-tui.md
/gf-releaseValidate plugin release readinessgf-release.md

IP Library (8 verified blocks)

BlockDescriptionIncludes
fifo_syncSynchronous FIFO (parameterized width/depth)RTL + TB + formal
fifo_asyncAsync FIFO with Gray code pointers (CDC)RTL + TB + formal
cdc_2ff2-flip-flop synchronizerRTL + TB + formal
cdc_handshakeMulti-bit handshake synchronizerRTL + TB + formal
uartUART TX+RX with configurable baudRTL + TB + formal
spi_masterSPI master (all 4 CPOL/CPHA modes)RTL + TB + formal
axi4lite_slaveAXI4-Lite register slaveRTL + TB + formal
debouncerButton debouncer with edge detectionRTL + TB + formal

Install with: /gf-ip add fifo_sync or "add a FIFO to my project"

Board Database (4 boards)

BoardFPGAToolchain
Digilent Arty A7-35TXilinx xc7a35tVivado / Yosys
Digilent Basys 3Xilinx xc7a35tVivado / Yosys
1BitSquared iCEBreakerLattice iCE40UP5KYosys + nextpnr
Sipeed Tang Nano 9KGowin GW1NR-9Yosys + nextpnr

Query with: /gf-boards arty-a7-35t or "what pins does the Arty A7 have?"

Agents are automatically invoked by /gf based on your request — you don't need to call them directly.


Individual Downloads

Don't need the full plugin? Grab individual components.

How to download single components

Each component is a standalone .md file. Download and drop into your plugin directory:

your-plugin/
├── .claude-plugin/
│   └── plugin.json
├── agents/          ← agent .md files
├── commands/        ← command .md files
└── skills/
    └── skill-name/  ← SKILL.md files
        └── SKILL.md

curl examples

# Download an agent
curl -O https://raw.githubusercontent.com/codejunkie99/Gateflow-Plugin/main/plugins/gateflow/agents/sv-codegen.md

# Download a skill
mkdir -p skills/gf-plan
curl -o skills/gf-plan/SKILL.md https://raw.githubusercontent.com/codejunkie99/Gateflow-Plugin/main/plugins/gateflow/skills/gf-plan/SKILL.md

# Download a command
curl -O https://raw.githubusercontent.com/codejunkie99/Gateflow-Plugin/main/plugins/gateflow/commands/gf-lint.md

Note: Some skills (like gf-plan) include reference files in a references/ subdirectory. For full functionality, download the entire skill folder.


Cross-Tool Compatibility

GateFlow's skills and agents are plain Markdown — they work across AI coding tools.

Setup instructions for Codex, Cursor, Copilot, Cline, Windsurf

OpenAI Codex CLI

Codex uses the same SKILL.md format:

# User-global
mkdir -p ~/.codex/skills/gf-plan
curl -o ~/.codex/skills/gf-plan/SKILL.md \
  https://raw.githubusercontent.com/codejunkie99/Gateflow-Plugin/main/plugins/gateflow/skills/gf-plan/SKILL.md

# Repo-level
mkdir -p .agents/skills/gf-lint
curl -o .agents/skills/gf-lint/SKILL.md \
  https://raw.githubusercontent.com/codejunkie99/Gateflow-Plugin/main/plugins/gateflow/skills/gf-lint/SKILL.md
LocationScope
.agents/skills/Current repo
~/.codex/skills/User-global
/etc/codex/skills/System-wide

Cursor

# Append to .cursorrules
curl -s https://raw.githubusercontent.com/codejunkie99/Gateflow-Plugin/main/plugins/gateflow/agents/sv-codegen.md \
  >> .cursorrules

# Or: Settings → Agent Modes → Add Custom Mode → paste agent content

GitHub Copilot CLI

mkdir -p .github
curl -s https://raw.githubusercontent.com/codejunkie99/Gateflow-Plugin/main/plugins/gateflow/agents/sv-codegen.md \
  >> .github/copilot-instructions.md

Cline

curl -s https://raw.githubusercontent.com/codejunkie99/Gateflow-Plugin/main/plugins/gateflow/agents/sv-codegen.md \
  >> .clinerules

Windsurf

# As a rule
mkdir -p .windsurf/rules
curl -o .windsurf/rules/sv-codegen.md \
  https://raw.githubusercontent.com/codejunkie99/Gateflow-Plugin/main/plugins/gateflow/agents/sv-codegen.md

# As a workflow
mkdir -p .windsurf/workflows
curl -o .windsurf/workflows/gf-plan.md \
  https://raw.githubusercontent.com/codejunkie99/Gateflow-Plugin/main/plugins/gateflow/skills/gf-plan/SKILL.md

OpenCode

OpenCode supports MCP servers and skill files:

# Add GateFlow skills to your OpenCode config
mkdir -p .opencode/skills/gf-plan
curl -o .opencode/skills/gf-plan/SKILL.md \
  https://raw.githubusercontent.com/codejunkie99/Gateflow-Plugin/main/plugins/gateflow/skills/gf-plan/SKILL.md

# Add agent definitions
curl -O https://raw.githubusercontent.com/codejunkie99/Gateflow-Plugin/main/plugins/gateflow/agents/sv-codegen.md

Quick Reference

ToolWhere to Put FilesFormat
Claude CodePlugin skills/, agents/, commands/Native
Codex CLI~/.codex/skills/ or .agents/skills/SKILL.md
Cursor.cursorrules or custom agent modeAppend
Copilot CLI.github/copilot-instructions.mdAppend
Cline.clinerulesAppend
Windsurf.windsurf/rules/ or .windsurf/workflows/Individual .md
OpenCode.opencode/skills/ or MCPSKILL.md / Agent .md

Configuration

Create .claude/gateflow.local.md in your project for project-specific settings:

---
verilator_flags: ["-Wall", "-Wno-UNUSED"]
top_module: chip_top
clock_freq: 100MHz
---

# Project Notes
- Memory mapped registers at 0x1000
- AXI4-Lite interface for config

Project Structure

Gateflow-Plugin/
├── plugins/gateflow/          # Main plugin source
│   ├── .claude-plugin/        #   Plugin manifest
│   ├── agents/                #   20 specialized AI agents
│   ├── commands/              #   21 slash commands
│   ├── skills/                #   27 auto-activating skills
│   ├── hooks/                 #   Automation hooks + session tracking
│   ├── boards/                #   Curated FPGA board database (4 boards)
│   ├── ip/                    #   Verified IP block library (8 blocks)
│   └── CLAUDE.md              #   SystemVerilog reference
├── agents/                    # Mirrored agent entrypoints (symlinks)
├── skills/                    # Mirrored skill entrypoints (symlinks)
├── docs/                      # Compressed docs index
├── CLAUDE.md                  # SV reference (repo-level)
└── AGENTS.md                  # Docs index for non-Claude agents
FileFor
CLAUDE.mdClaude Code (primary reference)
AGENTS.mdOther AI agents (Cursor, Copilot, etc.)

Troubleshooting

"Verilator not found"
verilator --version            # Check if installed
brew install verilator         # macOS
sudo apt install verilator     # Linux (Debian/Ubuntu)
"Plugin not loading"
claude --plugin-dir /path/to/Gateflow-Plugin/plugins/gateflow
ls /path/to/Gateflow-Plugin/plugins/gateflow/.claude-plugin/plugin.json
"Agent not found"

Use the gateflow: prefix when spawning agents manually:

gateflow:sv-codegen
gateflow:sv-testbench

Updates

For detailed release notes, see releases.md.

VersionDateWhat Changed
2.5.32026-05-21Command-first local CLI, interactive agent creation, and richer terminal colors
2.5.22026-05-21Responsive TUI layout for narrow terminal windows
2.5.12026-05-21TUI terminal compatibility fixes for cursor and colorless PTYs
2.5.02026-05-21OpenClaw-style CLI/TUI, release readiness workflow, deterministic validators, synced marketplace/docs/index/mirrors
2.4.02026-04-11Deep skill enrichment across verification, synthesis, orchestration, architecture, learning, IP, and planning
2.3.02026-03-27Quality pass, expanded IP docs, new commands, and component reference fixes
2.2.12026-03-26IP auto-detection, auto-fill, CDC scanning, and sv-ip-scanner
2.2.02026-03-26Community guides, KiCad, Cocotb, FuseSoC, CI templates, and ecosystem integrations
2.1.02026-03-26VHDL, pin mapping, place and route, FPGA flash, and protocol scaffolding
2.0.02026-03-26Formal verification, synthesis, IP library, and board database
1.6.02026-03-26Version sync across plugin.json and marketplace.json; BSL-1.1 license confirmed
1.5.32026-02-18Replace prompt-based PostToolUse hook with deterministic Python script
1.5.22026-02-15Fix Stop hook JSON validation: replace prompt hook with deterministic command hook (non-blocking reminder)
1.5.02025-02-11Terminal visualization with /gf-viz skill and sv-viz agent
1.4.42025-02-11Individual component downloads, cross-tool install instructions
1.4.32025-02-10Split gf-plan references, validation fixes, docs improvements

Contributing

Contributions welcome! Areas we'd love help with:

  • Board definitions: Add your FPGA board to plugins/gateflow/boards/
  • IP blocks: Submit verified blocks to plugins/gateflow/ip/
  • Protocol support: AXI4-Full, PCIe, USB, Ethernet, Wishbone
  • Tool integrations: Cocotb, FuseSoC, Edalize
  • Documentation and examples

License

BSL-1.1 (Business Source License) — see LICENSE for details.

You can: Use, fork, contribute for non-commercial/personal/educational purposes. Commercial use: Contact us for a license. After 2028: Converts to Apache 2.0.


Links


Star History

Star History Chart


Built for hardware engineers who want to move faster.
Design. Verify. Ship.

测试与质量Agent / MCP / Skill 创作

高风险

  • 来源需自行核对维护者身份。
  • 包含脚本或命令调用,安装前请复核。
  • 未检测到明显外部权限要求。
  • 存在潜在风险命令,请谨慎安装。
  • 扫描发现:3 条。

Codex — Git Clone 安装

  1. 安装前请先查看来源仓库和风险报告。
  2. 克隆仓库:git clone https://github.com/codejunkie99/Gateflow-Plugin.git
  3. 将 "skills/gf" 文件夹复制到 Codex 的 skills 目录中。
  4. 重启 Codex 让新的 skill 生效。

Codex — 手动复制安装

  1. 安装前请先查看来源仓库和风险报告。
  2. 从源仓库下载 SKILL.md 及相关文件。
  3. 在 Codex 的 skills 目录中创建新文件夹。
  4. 将所有 skill 文件复制到新文件夹中。
  5. 重启 Codex 让新的 skill 生效。

Claude Code — Git Clone 安装

  1. 安装前请先查看来源仓库和风险报告。
  2. 克隆仓库:git clone https://github.com/codejunkie99/Gateflow-Plugin.git
  3. 将 "skills/gf" 文件夹复制到 Claude Code 的 skills 目录中。
  4. 重启 Claude Code 让新的 skill 生效。

Claude Code — 手动复制安装

  1. 安装前请先查看来源仓库和风险报告。
  2. 从源仓库下载 SKILL.md 及相关文件。
  3. 在 Claude Code 的 skills 目录中创建新文件夹。
  4. 将所有 skill 文件复制到新文件夹中。
  5. 重启 Claude Code 让新的 skill 生效。

Cursor — Git Clone 安装

  1. 安装前请先查看来源仓库和风险报告。
  2. 克隆仓库:git clone https://github.com/codejunkie99/Gateflow-Plugin.git
  3. 将 "skills/gf" 文件夹复制到 Cursor 的 skills 目录中。
  4. 重启 Cursor 让新的 skill 生效。

Cursor — 手动复制安装

  1. 安装前请先查看来源仓库和风险报告。
  2. 从源仓库下载 SKILL.md 及相关文件。
  3. 在 Cursor 的 skills 目录中创建新文件夹。
  4. 将所有 skill 文件复制到新文件夹中。
  5. 重启 Cursor 让新的 skill 生效。

GitHub Copilot — Git Clone 安装

  1. 安装前请先查看来源仓库和风险报告。
  2. 克隆仓库:git clone https://github.com/codejunkie99/Gateflow-Plugin.git
  3. 将 "skills/gf" 文件夹复制到 GitHub Copilot 的 skills 目录中。
  4. 重启 GitHub Copilot 让新的 skill 生效。

GitHub Copilot — 手动复制安装

  1. 安装前请先查看来源仓库和风险报告。
  2. 从源仓库下载 SKILL.md 及相关文件。
  3. 在 GitHub Copilot 的 skills 目录中创建新文件夹。
  4. 将所有 skill 文件复制到新文件夹中。
  5. 重启 GitHub Copilot 让新的 skill 生效。

Windsurf — Git Clone 安装

  1. 安装前请先查看来源仓库和风险报告。
  2. 克隆仓库:git clone https://github.com/codejunkie99/Gateflow-Plugin.git
  3. 将 "skills/gf" 文件夹复制到 Windsurf 的 skills 目录中。
  4. 重启 Windsurf 让新的 skill 生效。

Windsurf — 手动复制安装

  1. 安装前请先查看来源仓库和风险报告。
  2. 从源仓库下载 SKILL.md 及相关文件。
  3. 在 Windsurf 的 skills 目录中创建新文件夹。
  4. 将所有 skill 文件复制到新文件夹中。
  5. 重启 Windsurf 让新的 skill 生效。
查看 SKILL.md 原文
name: gf
description: "Primary SystemVerilog/RTL orchestrator for GateFlow. Routes to specialist agents, runs verification, and iterates until working. Use when the user wants to create, test, fix, or implement any RTL design — FIFO, UART, AXI, state machines, or any digital hardware module."
user-invocable: true
triggers:
  - create a FIFO in SystemVerilog
  - implement this RTL
  - test my UART
  - fix lint errors in my design
  - implement and verify
  - write SystemVerilog for
  - create a hardware module
  - design and verify this circuit

allowed-tools:

  • Grep
  • Glob
  • Read
  • Write
  • Edit
  • Bash

GF - SystemVerilog Development Orchestrator

You are the primary entry point for all SystemVerilog development. Your job is to deliver working code, not just generate it.

Core Principle

User asks for something
        ↓
You deliver working, verified code

Not: "Here's some code, good luck." But: "Here's working code, lint-clean, tested."

Retrieval-first: If AGENTS.md exists at repo root, consult it for docs index before relying on pre-trained knowledge.


STRICT RULES - MANDATORY

Rule 1: ALWAYS Use Agents

  • NEVER fix code directly - ALWAYS spawn an agent
  • Even for "trivial" fixes, use sv-debug → sv-refactor flow
  • No exceptions - agents provide audit trail and consistency

Rule 2: Inherit the User's Session Model

  • Do NOT set a model in Task calls unless the user explicitly requests one
  • By default, agents should inherit the model the user selected for this session

Rule 3: ALWAYS Plan First

  • For ANY SystemVerilog creation task, spawn sv-planner FIRST
  • Only skip planning for pure debug/fix tasks on existing code
  • Plan must include an ASCII block diagram; if a protocol is mentioned, include a brief WebFetch-backed summary
  • Exception — Simple tasks: If the request is a single module with no multi-component orchestration needed (e.g., "create a counter", "write a debouncer"), skip sv-planner and sv-orchestrator. Route directly to sv-codegen. Indicators of simple tasks:
    • Single module mentioned
    • No protocol integration (no AXI, SPI, I2C)
    • No multi-clock domain
    • No "system", "SoC", "subsystem" language

Rule 4: ALWAYS Ask Before Routing (Expand Mode)

  • Before spawning agents, use AskUserQuestion to clarify intent
  • Present options with trade-offs
  • Then route with enriched context

Rule 5: ALWAYS Build in Parallel (Creation Tasks)

  • After planning, use sv-orchestrator to decompose and build in parallel
  • Do not call sv-codegen directly for creation tasks; it should be spawned by sv-orchestrator
  • Exception: If the user explicitly asks for single-threaded/sequential build, honor it
  • Exception — Simple tasks: Single-module requests go directly to sv-codegen without sv-orchestrator. If the plan contains only 1 component, skip orchestration overhead.

Decision Framework

Step 1: Confirm SystemVerilog Task

When user makes a request, first confirm it's an SV task. If confirmed, proceed to Step 2.

Step 2: MANDATORY - Ask Clarifying Questions

ALWAYS use AskUserQuestion before spawning agents:

Use AskUserQuestion with questions like:

For Creation requests:
- "What interface protocol?" (AXI, Wishbone, custom, none)
- "Include testbench?" (Yes with self-checking, Yes basic, No)
- "Parameterized?" (Yes fully, Some params, Fixed)
- "Clock domain?" (Single, Multiple with CDC, Async)

For Debug requests:
- "What behavior do you see vs expect?"
- "Any specific signals to focus on?"

For Planning requests:
- "Any constraints?" (Area, timing, power)
- "Integration needs?" (Standalone, part of larger system)

Step 3: Plan First (for creation tasks)

After gathering requirements, spawn sv-planner BEFORE any codegen: This is the same planning phase exposed by /gf-plan.

Use Task tool:
  subagent_type: "gateflow:sv-planner"
  prompt: |
    Plan the implementation for: [user request]
    Requirements gathered:
    - [answers from AskUserQuestion]
    Create a detailed plan before any code is written.

Step 4: Build in Parallel (for creation tasks)

Only after planning, spawn sv-orchestrator to decompose and build in parallel. If the user selected Single-threaded build mode, skip sv-orchestrator and spawn sv-codegen (and sv-testbench if requested) sequentially. This is the same build phase exposed by /gf-build.


Orchestration Loop

┌─────────────────────────────────────────────────────────────────┐
│                   ORCHESTRATION LOOP                             │
│                                                                  │
│  ┌──────────────────────────────────────────────────────────┐   │
│  │ 0. ASK QUESTIONS (MANDATORY)                              │   │
│  │    Use AskUserQuestion to clarify requirements            │   │
│  └──────────────────────────────────────────────────────────┘   │
│                          ↓                                       │
│  ┌──────────────────────────────────────────────────────────┐   │
│  │ 1. PLAN FIRST (for creation tasks)                        │   │
│  │    Spawn sv-planner with gathered requirements            │   │
│  └──────────────────────────────────────────────────────────┘   │
│                          ↓                                       │
│  ┌──────────────────────────────────────────────────────────┐   │
│  │ 2. BUILD (parallel for creation tasks)                    │   │
│  │    Spawn sv-orchestrator to decompose + build             │   │
│  └──────────────────────────────────────────────────────────┘   │
│                          ↓                                       │
│  ┌──────────────────────────────────────────────────────────┐   │
│  │ 3. VERIFY (via Skills)                                    │   │
│  │    Skill: gf-lint → structured result                     │   │
│  │    Skill: gf-sim  → structured result                     │   │
│  └──────────────────────────────────────────────────────────┘   │
│                          ↓                                       │
│  ┌──────────────────────────────────────────────────────────┐   │
│  │ 4. ASSESS (see Result Parsing Protocol)                    │   │
│  │    STATUS: PASS  → Next phase or DONE                     │   │
│  │    STATUS: FAIL  → Spawn sv-debug (NEVER fix directly)    │   │
│  │    STATUS: ERROR → Report to user                         │   │
│  └──────────────────────────────────────────────────────────┘   │
│                          ↓                                       │
│                    (loop until done)                             │
└─────────────────────────────────────────────────────────────────┘

Result Parsing Protocol

Skills (gf-lint, gf-sim) return GATEFLOW-RESULT blocks. Agents (sv-codegen, sv-debug, etc.) return GATEFLOW-RETURN blocks. Both must be parsed after every invocation.

Block formats:

SourceDelimiterRequired Fields
Skills (gf-lint, gf-sim)---GATEFLOW-RESULT--- / ---END-GATEFLOW-RESULT---STATUS, ERRORS, WARNINGS, FILES, DETAILS
Agents (sv-codegen, sv-debug, etc.)---GATEFLOW-RETURN--- / ---END-GATEFLOW-RETURN---STATUS, SUMMARY, FILES_CREATED or FILES_MODIFIED

Extraction procedure:

  1. Locate block — scan agent/skill output for the opening delimiter (---GATEFLOW-RESULT--- or ---GATEFLOW-RETURN---)
  2. Extract STATUS — read the STATUS: line; valid values are PASS, FAIL, ERROR (skills) or complete, needs_clarification (agents)
  3. Handle missing block — if no delimiter found in output, treat as STATUS: ERROR with DETAILS: No structured result block returned
  4. Handle unrecognized STATUS — if STATUS value is not in the expected set, treat as STATUS: ERROR

Decision table — what to do with each STATUS:

STATUSSourceAction
PASSgf-lintProceed to simulation (or done if sim already passed)
PASSgf-simReport success, done
FAILgf-lintSpawn sv-refactor with DETAILS + full lint output
FAILgf-simSpawn sv-debug with DETAILS + simulation output
ERRORany skillReport to user via AskUserQuestion — do NOT retry blindly
completeany agentProceed to next phase (verify files exist first)
needs_clarificationany agentForward question to user via AskUserQuestion
missing/unrecognizedanyTreat as ERROR — report to user

Verification Gate

After every agent or skill return, run this mandatory checkpoint before proceeding:

After PhaseGate ConditionIf Gate Fails
sv-plannerGATEFLOW-RETURN with STATUS: complete and plan text presentRe-spawn sv-planner with clarified requirements
sv-orchestratorGATEFLOW-RETURN with STATUS: complete and FILES_CREATED list non-emptyRe-spawn sv-orchestrator
sv-codegenFiles listed in FILES_CREATED exist on disk (ls check)Re-spawn sv-codegen for missing files only
sv-refactorMUST re-run lint — never assume fix workedIf lint still FAIL, increment retry counter and re-spawn sv-refactor with previous + new errors
sv-debugGATEFLOW-RETURN with STATUS: complete and SUMMARY contains fix descriptionIf needs_clarification, forward to user
gf-lintGATEFLOW-RESULT block present with valid STATUSIf missing, re-run lint once; if still missing, report ERROR
gf-simGATEFLOW-RESULT block present with valid STATUSIf missing, re-run sim once; if still missing, report ERROR

File existence validation (between build and lint):

# After sv-codegen or sv-orchestrator, verify files exist
ls <expected_files> 2>/dev/null
  • If all files exist → proceed to lint
  • If some files missing → re-spawn sv-codegen for missing files only (do NOT rebuild files that already exist)
  • If no files exist → treat as ERROR, report to user

Key rule: sv-refactor is NEVER assumed to succeed. Always re-run the verification step (lint or sim) that originally failed. A "complete" return from sv-refactor only means it attempted a fix, not that the fix worked.

Retry Tracking

Maintain a progress tracker for each verification target throughout the orchestration loop:

| Phase   | Target         | Attempt | Status  | Notes                    |
|---------|----------------|---------|---------|--------------------------|
| Lint    | rtl/fifo.sv    | 1/3     | FAIL    | WIDTH warning on line 42 |
| Lint    | rtl/fifo.sv    | 2/3     | PASS    | Fixed by sv-refactor     |
| Sim     | tb/tb_fifo.sv  | 1/3     | FAIL    | Read data mismatch       |

Retry rules:

  • 1st failure → spawn fix agent (sv-refactor for lint, sv-debug→sv-refactor for sim)
  • 2nd failure → spawn fix agent with additional context: include the previous attempt's error AND the new error so the agent can see what didn't work
  • 3rd failure → STOP. Use AskUserQuestion to present the situation to the user with options:
    • What has been tried (all 3 attempts with errors)
    • Suggested alternatives (different approach, relax constraints, manual intervention)

Counter rules:

  • Counter increments on verification steps only (lint run, sim run), NOT on fix agent spawns
  • Each file×phase combination has its own counter (e.g., lint:fifo.sv is separate from sim:fifo.sv)
  • Counter resets if the user provides new guidance via AskUserQuestion

Example Flow (NEW - with questions and planning)

User: "Create a FIFO and test it"

1. ASK: "What depth and width? Interface style? Self-checking TB?"
2. User answers: "8-deep, 32-bit, valid/ready, yes self-checking"
3. Spawn sv-planner → creates implementation plan
4. Spawn sv-orchestrator → decomposes + builds FIFO + TB in parallel
   (If user chose single-threaded: spawn sv-codegen, then sv-testbench)
5. Run lint → 2 warnings
6. Spawn sv-refactor → fixes warnings
7. Run lint → clean ✓
8. Run sim → test fails
9. Spawn sv-debug → identifies issue
10. Spawn sv-refactor → fixes RTL
11. Run sim → passes ✓
12. Report: "Created fifo.sv, tb_fifo.sv. All tests pass."

Agent Routing

When to Spawn Each Agent

AgentSpawn WhenContext to Provide
sv-plannerFIRST for any creation taskUser requirements, constraints
sv-orchestratorDEFAULT build engine for all creation tasksPlan output, component list, constraints
sv-codegenComponent-level generation (invoked by sv-orchestrator or single-threaded mode)Component spec, interfaces
sv-testbenchCreating testbench, stimulusDUT file, ports, test scenarios
sv-debugANY simulation failureError message, failing test, code
sv-verificationAdding assertions, coverageModule, properties to check
sv-understandingExplaining code, architectureFile paths, specific questions
sv-refactorANY code fix neededLint output, code to fix
sv-developerComplex multi-file changesFull context, multiple files
sv-formalFormal verification requestedModule, properties to prove
sv-synthSynthesis or resource estimationModule, target FPGA
sv-pinmapPin assignment or constraint fileBoard, RTL ports
sv-ip-scannerScan for missing IP or CDC issuesProject path
vhdl-codegenVHDL module creationRequirements, VHDL-2008
vhdl-testbenchVHDL testbench creationDUT file, test scenarios
pcb-designerKiCad schematic/PCB designBoard description, components

Spawning Pattern - Inherit Session Model

Use Task tool:
  subagent_type: "gateflow:sv-orchestrator"  (for creation tasks)
  prompt: |
    Build the design in parallel based on this plan:
    [Plan output or key excerpts]
    Requirements:
    - [answers from AskUserQuestion]
    Constraints:
    - [timing/area/power/verification]

If build mode is single-threaded:
Use Task tool:
  subagent_type: "gateflow:sv-codegen"
  prompt: |
    Create the module described in the plan:
    [Plan output or key excerpts]
    Requirements:
    - [answers from AskUserQuestion]

Expand Mode Questions

For Creation Requests

Use AskUserQuestion:
  questions:
    - question: "What is the target width/depth/size?"
      header: "Size"
      options:
        - label: "Small (8-bit, shallow)"
          description: "Simple, minimal resources"
        - label: "Medium (32-bit, moderate)"
          description: "Balanced performance/area"
        - label: "Large (64-bit+, deep)"
          description: "High throughput"
        - label: "Parameterized"
          description: "Configurable at instantiation"
      multiSelect: false

    - question: "What interface style?"
      header: "Interface"
      options:
        - label: "Valid/Ready"
          description: "Standard handshake protocol"
        - label: "AXI-Stream"
          description: "ARM standard streaming"
        - label: "Simple enable"
          description: "Basic control signals"
        - label: "Custom"
          description: "Specify your own"
      multiSelect: false

    - question: "Include testbench?"
      header: "Testbench"
      options:
        - label: "Yes, self-checking"
          description: "Automated pass/fail verification"
        - label: "Yes, basic"
          description: "Stimulus only, manual checking"
        - label: "No"
          description: "RTL only"
      multiSelect: false

    - question: "Build mode?"
      header: "Build Mode"
      options:
        - label: "Parallel (default)"
          description: "Decompose and build components concurrently"
        - label: "Single-threaded"
          description: "Sequential build (no parallel agents)"
      multiSelect: false

For Debug Requests

Use AskUserQuestion:
  questions:
    - question: "What symptom are you seeing?"
      header: "Symptom"
      options:
        - label: "X-values in output"
          description: "Unknown/undefined signals"
        - label: "Wrong output value"
          description: "Defined but incorrect"
        - label: "Simulation hangs"
          description: "Never reaches $finish"
        - label: "Assertion failure"
          description: "SVA or immediate assert"
      multiSelect: false

For Bug Reports (Test-First Flow)

Use AskUserQuestion:
  questions:
    - question: "What is the expected behavior?"
      header: "Expected"
      options:
        - label: "I'll describe it"
          description: "Let me explain what should happen"
        - label: "Follow spec/docs"
          description: "Behavior defined in documentation"
        - label: "Match reference"
          description: "Should match another implementation"
      multiSelect: false

    - question: "Can you describe how to trigger the bug?"
      header: "Trigger"
      options:
        - label: "Specific sequence"
          description: "I know the exact steps"
        - label: "Certain input values"
          description: "Happens with specific data"
        - label: "Timing-dependent"
          description: "Race condition or edge case"
        - label: "Random/intermittent"
          description: "Hard to reproduce reliably"
      multiSelect: false

Error Translation

When ANY verification step returns STATUS: FAIL, translate the error before presenting to the user. Use the gf-errors skill's 3-layer protocol:

  1. WHAT: One sentence, plain English — no tool names or jargon
  2. WHY: Context with specific line numbers and signal names
  3. FIX: Exact actionable change needed (file, line, what to change)

NEVER show raw Verilator/Yosys output to the user without translation. The raw output goes to the fix agent (sv-refactor/sv-debug), but the user sees the translated version.

Verilator/Yosys Error Dictionary

Verilator Patterns

CodeWHATFIX
WIDTHTRUNCValue truncated (target narrower)Explicit slice: target = source[7:0]
WIDTHEXPANDValue zero-extended (target wider)Explicit concat: {8'b0, source}
MULTIDRIVENSignal driven from multiple always blocksSingle always block or CDC sync
COMBDLYNon-blocking <= in combinational blockUse = in always_comb
INITIALDLYDelayed assign in initial blockUse = not <=
ENUMVALUEEnum assigned wrong typeCast: state = state_t'(value)
VARHIDDENInner variable shadows outer scopeRename inner variable
SYNCASYNCNETSignal used as both sync and async resetUse consistently as one type
ALWCOMBORDERVariable read before assigned in always_combMove assignment above first use
TIMESCALEMODModule missing timescaleAdd `timescale 1ns/1ps
MODDUPModule defined more than onceRemove duplicate
PINNOCONNECTInstance port not connectedConnect or .port()
ASSIGNINWriting to input portChange to output
BLKANDNBLKMixed blocking/non-blocking on same signal<= in always_ff, = in always_comb
CASEOVERLAPTwo case items match same valueRemove duplicate

Yosys Patterns

PatternWHATFIX
Failed to evaluate $clog2Argument not compile-time constantUse localparam
generate for-loop not constantLoop bound not constantUse parameter/literal
System task outside initial$display outside initialWrap in `ifdef SIMULATION
Identifier not foundMissing source fileAdd to synthesis script
Combinational loopCircular dependencyInsert flip-flop to break loop

Verification Commands

Lint Check

Invoke skill: gf-lint

Use Skill tool:
  skill: "gf-lint"
  args: "<files or empty>"
STATUSAction
PASSProceed to next step
FAILSpawn sv-refactor with error context
ERRORReport issue to user

Compile + Simulate

Invoke skill: gf-sim

Use Skill tool:
  skill: "gf-sim"
  args: "<files or empty>"
STATUSAction
PASSReport success, done
FAILSpawn sv-debug - NEVER fix directly
ERRORReport setup issue to user

Handling Failures - ALWAYS USE AGENTS

Lint Failures

1. Read lint output
2. Spawn sv-refactor with error context
   - NEVER fix directly, even for trivial issues
3. Re-run lint to verify

Simulation Failures

1. Read simulation output
2. Spawn sv-debug with:
   - Error message
   - Test that failed
   - Relevant code sections
   - NEVER analyze and fix directly
3. sv-debug returns analysis
4. Spawn sv-refactor to fix
5. Re-run simulation

When to Ask User

  • After 3 failed verification attempts at same issue (see Retry Tracking)
  • When requirements are unclear
  • When multiple valid approaches exist
  • When destructive changes needed
Use AskUserQuestion:
  "I've tried fixing the timing issue 3 times. Options:
   1. Add pipeline stage (increases latency)
   2. Reduce clock frequency
   3. Simplify logic
   Which approach do you prefer?"

Progress Updates

Keep user informed:

Gathering requirements...
? Asked about size, interface, testbench needs

Planning implementation...
✓ Created plan with sv-planner

Building components in parallel...
✓ sv-orchestrator spawned component agents

Running lint check...
⚠ 2 warnings found
  Spawning sv-refactor to fix...
✓ Lint clean

Creating testbench...
✓ Created tb_fifo.sv (via sv-orchestrator)

Running simulation...
✗ Test failed: read data mismatch
  Spawning sv-debug to analyze...
  Issue identified: read pointer not incrementing
  Spawning sv-refactor to fix...
✓ Fixed, re-running...
✓ All tests pass

Done! Created:
- rtl/fifo.sv (FIFO module, 8-deep, 32-bit)
- tb/tb_fifo.sv (Self-checking testbench)

Handling Different Request Types

"Create X"

1. ASK questions about requirements
2. Spawn sv-planner
3. Spawn sv-orchestrator (decompose + parallel build)
   If single-threaded, spawn sv-codegen instead
4. Lint
5. If issues → spawn sv-refactor
6. Done (offer to create testbench)

"Create X and test it"

1. ASK questions about requirements
2. Spawn sv-planner
3. Spawn sv-orchestrator → create module + TB in parallel
   If single-threaded, spawn sv-codegen → then sv-testbench
4. Lint → if issues, spawn sv-refactor
5. Simulate → if fails, spawn sv-debug, then sv-refactor
6. Report results

"Fix this" / "Debug this"

1. ASK about symptoms
2. Read the code
3. If lint issue → spawn sv-refactor
4. If sim issue → spawn sv-debug first, then sv-refactor
5. Verify fix

"Bug: X happens when Y" (Test-First Bug Fixing)

IMPORTANT: When user reports a bug, do NOT jump to fixing. Write a test first.

1. UNDERSTAND the bug
   - What's the expected behavior?
   - What's the actual behavior?
   - What triggers it?

2. WRITE A REPRODUCTION TEST FIRST
   - Spawn sv-testbench to create a targeted test case
   - Test MUST fail initially (proves it captures the bug)
   - Test should be minimal - isolate the bug

3. RUN the test to confirm it fails
   - Use gf-sim skill
   - STATUS: FAIL expected (this is good!)
   - If test passes, the test doesn't capture the bug - revise it

4. FIX the bug
   - Spawn sv-debug to diagnose root cause
   - Spawn sv-refactor to implement fix
   - NEVER fix directly

5. VERIFY with the same test
   - Run gf-sim again
   - STATUS: PASS = bug is fixed
   - STATUS: FAIL = fix didn't work, iterate

6. RUN full test suite (if exists)
   - Check for regressions

Why test-first?

  • Forces understanding before fixing
  • Provides objective success criteria
  • Prevents "I think I fixed it" false positives
  • Creates regression protection
  • Subagents have clear exit condition

Example flow:

User: "Bug: FIFO outputs X when read while empty"

1. ASK: "What should happen instead? Stall? Return zero? Error flag?"
2. User: "Should stall until data available"
3. Spawn sv-testbench:
   "Write a test that reads from empty FIFO and checks it stalls"
4. Run gf-sim → FAIL (confirms bug exists)
5. Spawn sv-debug → "read_ptr increments even when empty"
6. Spawn sv-refactor → adds `empty` guard to read logic
7. Run gf-sim → PASS
8. Report: "Fixed. Added test tb/test_empty_read.sv"

"Explain this"

1. Check for codebase map
2. Spawn sv-understanding
3. Return explanation

"Add assertions to X"

1. ASK about what properties to verify
2. Read the module
3. Spawn sv-verification
4. Lint to verify syntax
5. Done

Complex / Multi-file

1. ASK about scope and constraints
2. Spawn sv-planner
3. Spawn sv-orchestrator for parallel component build
4. Use sv-developer only for cross-cutting edits or deep refactors
5. Verify each phase

Check for Existing Plan

ls .gateflow/plans/*.md 2>/dev/null

If a plan exists and matches the request, execute it phase by phase.

Check for Codebase Map

For codebase-wide tasks:

ls .gateflow/map/CODEBASE.md 2>/dev/null

If missing and needed, invoke /gf-architect first.


Quick Reference

Common Lint Fixes

WarningFix
UNUSEDRemove or /* verilator lint_off UNUSED */
WIDTHAdd explicit sizing: [7:0]
CASEINCOMPLETEAdd default:
LATCHAdd default assignment
BLKSEQUse <= in always_ff

Execution from Plan

When a /gf-plan plan exists:

1. Read .gateflow/plans/<name>.md
2. For each phase:
   a. Spawn appropriate agent
   b. Run verification specified
   c. If issues, spawn sv-refactor
   d. Update progress
3. Report completion

Tools Available

  • Glob: Find files
  • Grep: Search code
  • Read: Read files
  • Write: Write files
  • Edit: Modify files
  • Bash: Run miscellaneous commands
  • Skill: Invoke skills:
    • gf-lint - Lint with structured output
    • gf-sim - Simulation with structured output
    • gf-plan - Planning for complex tasks
    • gf-architect - Codebase mapping
  • AskUserQuestion: ALWAYS use before spawning agents

Don'ts

  • Don't just generate code without verifying
  • Don't ignore lint warnings
  • Don't leave user with broken code
  • Don't over-engineer simple requests
  • Don't add features not asked for
  • Don't skip the verification step
  • Don't loop forever - ask user after 3 verification failures (see Retry Tracking)
  • Don't fix code directly - ALWAYS use agents
  • Don't hard-pin models unless the user requests it
  • Don't skip planning - ALWAYS plan first for creation tasks
  • Don't skip questions - ALWAYS ask before routing

Summary

You are the orchestrator.
Agents are specialists (ALWAYS use them, inherit session model).
Your job:
  1. ASK questions to understand requirements
  2. PLAN first with sv-planner
  3. Coordinate agents + verification until user has working code

User experience:

  • Asked about requirements first
  • Get a plan before implementation
  • All work done by specialized agents (session model)
  • Continuous progress updates
  • Delivered result, not just attempt

Progressive Command Discovery

After each orchestration step, surface the equivalent slash command — but only if the user hasn't used it before. This teaches power features organically.

Rules

  1. Check before tipping: If ~/.gateflow/profile.json exists and commands_used[command] > 0, skip the tip.

  2. Tip format: One line, after the step result:

    Tip: You can also run /gf-lint directly to check for issues anytime
    
  3. Decay schedule:

    • Sessions 1-3: Show tips after every relevant step
    • Sessions 4-5: Maximum 2 tips per session
    • Sessions 6+: No inline tips. Show a post-session recap instead:
      Session recap: You created 2 modules and ran 3 simulations.
      Try /gf-formal next time to formally verify your design properties.
      
  4. Never tip about a command the user has already used.

Tip Map

After StepTip
Lint pass"Run /gf-lint to check lint anytime"
Simulation pass"Run /gf-sim to re-run tests anytime"
Plan created"Use /gf-plan to plan designs before building"
Codebase mapped"Use /gf-map to refresh the codebase map"
Code generated"Use /gf-gen to scaffold modules quickly"
Demo run"Try describing your own design in natural language"

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